In the case of conventional cache memories, data is read from the bit lines driven with a weak current of each memory cell and the weak signal is amplified by a sense amplifier.
Usually, when a potential difference between two bit lines is 100 mV, the sense amplifier is enabled. However, because the time of reading from such a cache memory is less when the sense amplifier is enabled with a potential difference lower than 100 mV, the performance of the cache memory is improved. If the sense amplifier is enabled with an extremely small potential difference, however, the amplification will malfunction; a correct value is not amplified and a wrong value is output if the current in a memory cell is reduced with a process variation or if an offset occurs in the threshold voltage of an input MOS transistor of the sense amplifier. More concretely, it is very important to decide the time for enabling the sense amplifier when in designing.
Conventionally, the timing for enabling the sense amplifier is changed and measured, thereby deciding the optimized timing by processing the metallic line of the sense amplifier with the use of a focused ion beam (FIB) after a trial cache memory is formed on a silicon wafer. If the FIB is used, however, only one timing is set for one chip. In addition, a whole day is required for the processing.
On the other hand, a conventional well-known technique for such a timing decision is disclosed in ICCSS Digest of Technical Papers (pp. 236-237) 1998. This document describes that the timing of the object programmable cache memory is changed after the manufacturing.
Although conventional example publicly known is only in theory and unworkable in practice, the present inventor et al has found, as a result of a preliminary examination that a long time is required for testing the memory from external in the on-chip timing adjustment on the basis of the conventional technique and this causes many processes to be needed for finding operation conditions of the object LSI.
More concretely, there has been no well-known means for operating an LSI provided with an on-chip memory using an element whose process condition is uncertain so as not to be controlled (or to be controlled less) from external (ex., an IC tester).
Furthermore, there is no well-known method for adjusting such a timing to a production variation after the chip is manufactured if a CPU, a cache memory, and a DRAM used as a secondary cache are used together.